#
# This class.ptf file built by Component Editor
# 2008.02.19.16:45:25
#
# DO NOT MODIFY THIS FILE
# If you hand-modify this file you will likely
# interfere with Component Editor's ability to
# read and edit it. And then Component Editor
# will overwrite your changes anyway. So, for
# the very best results, just relax and
# DO NOT MODIFY THIS FILE
#
CLASS eth_ocm
{
   CB_GENERATOR 
   {
      HDL_FILES 
      {
         FILE 
         {
            use_in_simulation = "1";
            use_in_synthesis = "1";
            type = "verilog";
            filepath = "eth_ocm.v";
         }

      }
      top_module_name = "eth_ocm.v:eth_ocm";
      emit_system_h = "0";
   }
   MODULE_DEFAULTS global_signals
   {
      class = "eth_ocm";
      class_version = "8.0";
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Has_Clock = "1";
         Top_Level_Ports_Are_Enumerated = "1";
      }
      COMPONENT_BUILDER 
      {
         GLS_SETTINGS 
         {
         }
      }
      PORT_WIRING 
      {
         PORT av_clk
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "clk";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT av_reset
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "reset";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT mtx_clk_pad_i
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT mtxd_pad_o
         {
            width = "4";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT mtxen_pad_o
         {
            width = "1";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT mtxerr_pad_o
         {
            width = "1";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT mrx_clk_pad_i
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT mrxd_pad_i
         {
            width = "4";
            width_expression = "";
            direction = "input";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT mrxdv_pad_i
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT mrxerr_pad_i
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT mcoll_pad_i
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT mcrs_pad_i
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT mdc_pad_o
         {
            width = "1";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT md_pad_i
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT md_pad_o
         {
            width = "1";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT md_padoe_o
         {
            width = "1";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Is_Ethernet_Mac = "1";
         hdl_parameters 
         {
            total_descriptors = "128";
            tx_fifo_size_in_bytes = "128";
            rx_fifo_size_in_bytes = "4096";
         }
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL x101
            {
               name = "eth_ocm/global_signals";
               format = "Divider";
            }
            SIGNAL x102
            {
               name = "av_clk";
            }
            SIGNAL x103
            {
               name = "av_reset";
            }
            SIGNAL x104
            {
               name = "mtx_clk_pad_i";
            }
            SIGNAL x105
            {
               name = "mtxd_pad_o";
               radix = "hexadecimal";
            }
            SIGNAL x106
            {
               name = "mtxen_pad_o";
            }
            SIGNAL x107
            {
               name = "mtxerr_pad_o";
            }
            SIGNAL x108
            {
               name = "mrx_clk_pad_i";
            }
            SIGNAL x109
            {
               name = "mrxd_pad_i";
               radix = "hexadecimal";
            }
            SIGNAL x110
            {
               name = "mrxdv_pad_i";
            }
            SIGNAL x111
            {
               name = "mrxerr_pad_i";
            }
            SIGNAL x112
            {
               name = "mcoll_pad_i";
            }
            SIGNAL x113
            {
               name = "mcrs_pad_i";
            }
            SIGNAL x114
            {
               name = "mdc_pad_o";
            }
            SIGNAL x115
            {
               name = "md_pad_i";
            }
            SIGNAL x116
            {
               name = "md_pad_o";
            }
            SIGNAL x117
            {
               name = "md_padoe_o";
            }
            SIGNAL x118
            {
               name = "eth_ocm/control_port";
               format = "Divider";
            }
            SIGNAL x119
            {
               name = "av_address";
               radix = "hexadecimal";
            }
            SIGNAL x120
            {
               name = "av_read";
            }
            SIGNAL x121
            {
               name = "av_readdata";
               radix = "hexadecimal";
            }
            SIGNAL x122
            {
               name = "av_write";
            }
            SIGNAL x123
            {
               name = "av_writedata";
               radix = "hexadecimal";
            }
            SIGNAL x124
            {
               name = "av_chipselect";
            }
            SIGNAL x125
            {
               name = "av_waitrequest_n";
            }
            SIGNAL x126
            {
               name = "av_irq";
            }
            SIGNAL x127
            {
               name = "eth_ocm/rx_master";
               format = "Divider";
            }
            SIGNAL x128
            {
               name = "av_rx_address";
               radix = "hexadecimal";
            }
            SIGNAL x129
            {
               name = "av_rx_waitrequest";
            }
            SIGNAL x130
            {
               name = "av_rx_write";
            }
            SIGNAL x131
            {
               name = "av_rx_writedata";
               radix = "hexadecimal";
            }
            SIGNAL x132
            {
               name = "av_rx_byteenable";
               radix = "hexadecimal";
            }
            SIGNAL x133
            {
               name = "eth_ocm/tx_master";
               format = "Divider";
            }
            SIGNAL x134
            {
               name = "av_tx_address";
               radix = "hexadecimal";
            }
            SIGNAL x135
            {
               name = "av_tx_read";
            }
            SIGNAL x136
            {
               name = "av_tx_waitrequest";
            }
            SIGNAL x137
            {
               name = "av_tx_readdata";
               radix = "hexadecimal";
            }
            SIGNAL x138
            {
               name = "av_tx_readdatavalid";
            }
         }
      }
      SLAVE control_port
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Address_Group = "1";
            Has_Clock = "0";
            Address_Width = "10";
            Address_Alignment = "native";
            Data_Width = "32";
            Has_Base_Address = "1";
            Has_IRQ = "1";
            Setup_Time = "0";
            Hold_Time = "0";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Read_Latency = "0";
            Maximum_Pending_Read_Transactions = "0";
            Active_CS_Through_Read_Latency = "0";
            Is_Printable_Device = "0";
            Is_Memory_Device = "0";
            Is_Readable = "1";
            Is_Writable = "1";
            Minimum_Uninterrupted_Run_Length = "1";
         }
         COMPONENT_BUILDER 
         {
            AVS_SETTINGS 
            {
               Setup_Value = "0";
               Read_Wait_Value = "0";
               Write_Wait_Value = "0";
               Hold_Value = "0";
               Timing_Units = "cycles";
               Read_Latency_Value = "0";
               Minimum_Arbitration_Shares = "1";
               Active_CS_Through_Read_Latency = "0";
               Max_Pending_Read_Transactions_Value = "1";
               Address_Alignment = "native";
               Is_Printable_Device = "0";
               Interleave_Bursts = "0";
               interface_name = "Avalon Slave";
               external_wait = "1";
               Is_Memory_Device = "0";
            }
         }
         PORT_WIRING 
         {
            PORT av_address
            {
               width = "10";
               width_expression = "";
               direction = "input";
               type = "address";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT av_read
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "read";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT av_readdata
            {
               width = "32";
               width_expression = "";
               direction = "output";
               type = "readdata";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT av_write
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "write";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT av_writedata
            {
               width = "32";
               width_expression = "";
               direction = "input";
               type = "writedata";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT av_chipselect
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "chipselect";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT av_waitrequest_n
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "waitrequest_n";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT av_irq
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "irq";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
         }
      }
      MASTER rx_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Address_Group = "2";
            Has_Clock = "0";
            Address_Width = "32";
            Data_Width = "32";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Is_Asynchronous = "0";
            Has_IRQ = "0";
            Irq_Scheme = "none";
            Interrupt_Range = "";
            Is_Readable = "0";
            Is_Writable = "1";
            Is_Big_Endian = "0";
            Register_Outgoing_Signals = "0";
         }
         COMPONENT_BUILDER 
         {
            AVM_SETTINGS 
            {
               stream_reads = "0";
               stream_writes = "0";
               irq_width = "0";
               irq_number_width = "0";
               irq_scheme = "none";
               Is_Asynchronous = "0";
               Is_Big_Endian = "0";
            }
         }
         PORT_WIRING 
         {
            PORT av_rx_address
            {
               width = "32";
               width_expression = "";
               direction = "output";
               type = "address";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT av_rx_waitrequest
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "waitrequest";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT av_rx_write
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "write";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT av_rx_writedata
            {
               width = "32";
               width_expression = "";
               direction = "output";
               type = "writedata";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT av_rx_byteenable
            {
               width = "4";
               width_expression = "";
               direction = "output";
               type = "byteenable";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
         }
      }
      MASTER tx_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Address_Group = "3";
            Has_Clock = "0";
            Address_Width = "32";
            Data_Width = "32";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Is_Asynchronous = "0";
            Has_IRQ = "0";
            Irq_Scheme = "none";
            Interrupt_Range = "";
            Is_Readable = "1";
            Is_Writable = "0";
            Is_Big_Endian = "0";
            Register_Outgoing_Signals = "0";
         }
         COMPONENT_BUILDER 
         {
            AVM_SETTINGS 
            {
               stream_reads = "0";
               stream_writes = "0";
               irq_width = "0";
               irq_number_width = "0";
               irq_scheme = "none";
               Is_Asynchronous = "0";
               Is_Big_Endian = "0";
            }
         }
         PORT_WIRING 
         {
            PORT av_tx_address
            {
               width = "32";
               width_expression = "";
               direction = "output";
               type = "address";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT av_tx_read
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "read";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT av_tx_waitrequest
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "waitrequest";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT av_tx_readdata
            {
               width = "32";
               width_expression = "";
               direction = "input";
               type = "readdata";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT av_tx_readdatavalid
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "readdatavalid";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
         }
      }
   }
   USER_INTERFACE 
   {
      USER_LABELS 
      {
         name = "OpenCores 10/100 Ethernet MAC Avalon";
         technology = "Interface Protocols/Ethernet";
      }
      WIZARD_UI the_wizard_ui
      {
         title = "OpenCores 10/100 Ethernet MAC Avalon - {{ $MOD }}";
         CONTEXT 
         {
            H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters";
            M = "";
            SBI_global_signals = "SYSTEM_BUILDER_INFO";
            SBI_control_port = "SLAVE control_port/SYSTEM_BUILDER_INFO";
            SBI_rx_master = "MASTER rx_master/SYSTEM_BUILDER_INFO";
            SBI_tx_master = "MASTER tx_master/SYSTEM_BUILDER_INFO";
         }
         PAGES main
         {
            PAGE 1
            {
               align = "left";
               title = "<b>eth_ocm 7.2</b> Settings";
               layout = "vertical";
               TEXT 
               {
                  title = "Built on: 2008.02.19.16:45:25";
               }
               TEXT 
               {
                  title = "Class name: eth_ocm";
               }
               TEXT 
               {
                  title = "Class version: 7.2";
               }
               TEXT 
               {
                  title = "Component name: eth_ocm";
               }
               TEXT 
               {
                  title = "Component Group: Interface Protocols/Ethernet";
               }
               GROUP parameters
               {
                  title = "Parameters";
                  layout = "form";
                  align = "left";
                  EDIT e1
                  {
                     id = "TOTAL_DESCRIPTORS";
                     editable = "1";
                     title = "TOTAL_DESCRIPTORS:";
                     columns = "40";
                     tooltip = "default value: 128";
                     DATA 
                     {
                        $H/total_descriptors = "$";
                     }
                     q = "'";
                     warning = "{{ if(!(regexp('ugly_'+$H/total_descriptors,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/total_descriptors,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/total_descriptors,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/total_descriptors,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/total_descriptors,'ugly_-?[0-9]+')))'TOTAL_DESCRIPTORS must be numeric constant, not '+$H/total_descriptors; }}";
                  }
                  EDIT e2
                  {
                     id = "TX_FIFO_SIZE_IN_BYTES";
                     editable = "1";
                     title = "TX_FIFO_SIZE_IN_BYTES:";
                     columns = "40";
                     tooltip = "default value: 128";
                     DATA 
                     {
                        $H/tx_fifo_size_in_bytes = "$";
                     }
                     q = "'";
                     warning = "{{ if(!(regexp('ugly_'+$H/tx_fifo_size_in_bytes,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/tx_fifo_size_in_bytes,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/tx_fifo_size_in_bytes,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/tx_fifo_size_in_bytes,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/tx_fifo_size_in_bytes,'ugly_-?[0-9]+')))'TX_FIFO_SIZE_IN_BYTES must be numeric constant, not '+$H/tx_fifo_size_in_bytes; }}";
                  }
                  EDIT e3
                  {
                     id = "RX_FIFO_SIZE_IN_BYTES";
                     editable = "1";
                     title = "RX_FIFO_SIZE_IN_BYTES:";
                     columns = "40";
                     tooltip = "default value: 4096";
                     DATA 
                     {
                        $H/rx_fifo_size_in_bytes = "$";
                     }
                     q = "'";
                     warning = "{{ if(!(regexp('ugly_'+$H/rx_fifo_size_in_bytes,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/rx_fifo_size_in_bytes,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/rx_fifo_size_in_bytes,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/rx_fifo_size_in_bytes,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/rx_fifo_size_in_bytes,'ugly_-?[0-9]+')))'RX_FIFO_SIZE_IN_BYTES must be numeric constant, not '+$H/rx_fifo_size_in_bytes; }}";
                  }
               }
            }
         }
      }
   }
   SOPC_Builder_Version = "7.20";
   COMPONENT_BUILDER 
   {
      HDL_PARAMETERS 
      {
         # generated by CBDocument.getParameterContainer
         # used only by Component Editor
         HDL_PARAMETER total_descriptors
         {
            parameter_name = "TOTAL_DESCRIPTORS";
            type = "integer";
            default_value = "128";
            editable = "1";
            tooltip = "";
         }
         HDL_PARAMETER tx_fifo_size_in_bytes
         {
            parameter_name = "TX_FIFO_SIZE_IN_BYTES";
            type = "integer";
            default_value = "128";
            editable = "1";
            tooltip = "";
         }
         HDL_PARAMETER rx_fifo_size_in_bytes
         {
            parameter_name = "RX_FIFO_SIZE_IN_BYTES";
            type = "integer";
            default_value = "4096";
            editable = "1";
            tooltip = "";
         }
      }
      SW_FILES 
      {
      }
      built_on = "2008.02.19.16:45:25";
      CACHED_HDL_INFO 
      {
         # cached hdl info, emitted by CBFrameRealtime.getDocumentCachedHDLInfoSection
         # used only by Component Builder
      }
   }
   ASSOCIATED_FILES 
   {
      Add_Program = "the_wizard_ui";
      Edit_Program = "the_wizard_ui";
      Generator_Program = "cb_generator.pl";
   }
}